The present invention relates generally to cell-based design using deep sub-micron devices. Still more particularly, the present disclosure relates to the methodology of incorporating mixed multi-Vt devices in deep sub-micron standard cells, thereby increasing overall performance and reducing power dissipation. With granularity of multi-Vt devices down to transistor level, rather than cell level, a cell-based design can approach the speed and power performance of a full custom design.
Semiconductor technology is evolving into the very deep sub-micron geometries of less than 100 nanometers (nm) to integrate more complex functionality at higher performance on a single chip. This technology is needed to produce the complex system-on-chip (SOC) designs required for today's portable devices such as cellular telephones, laptops, and other electronic devices. Since these portable devices use batteries, the chip power dissipation has become as critical a factor as circuit performance or speed.
Sub-100 nm devices offer more complex functionality and higher performance, but not without a cost. It has been observed that when the transistor channel length is small enough, current continues to flow even during standby states because of leakage. As such, power is unnecessarily dissipated in these nanometer geometry designs, thereby draining battery power. The tradeoff between chip performance and power dissipation is becoming an increasingly important issue in deep sub-micron designs.
The increased power dissipation of sub-100 nm devices is due to an effect called “sub-threshold conduction”. When the gate-source voltage (Vgs) of a sub-micron gate is lower than its threshold voltage (Vt), it is in the sub-threshold region. This can be characterized by a logarithmic change in drain current with a change in Vgs until this device is completely turned off. Previous semiconductor above-100 nm devices had higher Vt such that the drain current was insignificant when Vgs=0. In sub-100 nm devices, threshold voltage Vt is so low, when Vgs=0 or during standby states, that drain current becomes significant. Other than subthreshold voltage effect, punch-through can also cause device leakage. The very thin gate oxide for very deep sub-micron devices also increases gate leakage current.
To counter this issue, manufacturers have created sub-100 nm devices with higher Vt (high-Vt devices), but these devices are slower and can affect chip speed and performance. In a typical 90 nm process, a device with lower Vt (low-Vt device) would have sub-threshold leakage current of approximately 10 nA/um, while a high-Vt device would have sub-threshold leakage current of approximately 1 nA/um. Therefore, the power dissipation may be reduced by a factor of ten if a high-Vt device is used in place of a low-Vt device. However, the circuit performance may not meet its requirements due to the lower speed of the high-Vt devices. A tradeoff of performance and power dissipation must be made to meet both speed and power constraints in sub-100 nm designs.
Circuits are conventionally designed by using circuit cells, which are basic building blocks that have all transistors contained therein with the same transistor properties. The transistors in a cell are either all high-Vt devices or all low-Vt devices, and there is no standard cell available that can accommodate devices with different threshold properties to maximize the functions of the cell.
Desirable in the art of cell design are additional methodologies that may utilize mixed low-Vt and high-Vt devices, such that a tradeoff of both the chip performance and power dissipation criteria may be performed and optimized.